1. Field of the Invention
This invention relates to computer systems. More particularly, this invention relates to a method and circuit for shifting the level of a differential clock crossing point.
2. Description of the Related Art
Computer system technology is rapidly advancing, enabling computer systems to operate at ever-increasing speeds. As microprocessor speeds increase, memory speeds should also increase. Otherwise, the memory will become a system bottleneck. Overall system performance will be lowered if processors are forced to waste their newly-gained speed waiting on memory. Unfortunately, memory speeds have not necessarily kept pace with processor speeds. The growing gap between processor and memory speed is becoming more of a concern as software becomes increasingly memory intensive.
One recent memory improvement is DDR SDRAM. DDR SDRAM (double data rate synchronous dynamic random access memory) is a type of SDRAM that supports data transfers on both edges of each clock cycle. By transferring data on both the rising and failing edges of the clock, DDR SDRAM effectively doubles the memory chip""s data throughput. At the same time, DDR SDRAM is enough like older memory technology to allow designers to reuse some of the same testing equipment, basic motherboard technology and packaging that the older technology used. Furthermore, competing technology RDRAM (Rambus DRAM) uses a propriety standard while DDR SDRAM has an open standard. These features make DDR DRAM a desirable component in today""s computer systems.
Turning now to FIG. 1, a block diagram of one embodiment of a computer system 100 including processor 10 coupled to a variety of system components through a bus bridge 102 is shown. Other embodiments are possible and contemplated. In the depicted system, a main memory 104 is coupled to bus bridge 102 through a memory bus 106, and a graphics controller 108 is coupled to bus bridge 102 through an AGP bus 110. Finally, a plurality of PCI devices 112A-112B are coupled to bus bridge 102 through a PCI bus 114. A secondary bus bridge 116 may further be provided to accommodate an electrical interface to one or more EISA or ISA devices 118 through an EISA/ISA bus 120. Processor 10 is coupled to bus bridge 102 through a CPU bus 124 and to an optional L2 cache 128.
Bus bridge 102 provides an interface between processor 10, main memory 104, graphics controller 108, and devices attached to PCI bus 114. When an operation is received from one of the devices connected to bus bridge 102, bus bridge 102 identifies the target of the operation (e.g. a particular device or, in the case of PCI bus 114, that the target is on PCI bus 114). Bus bridge 102 routes the operation to the targeted device. Bus bridge 102 generally translates an operation from the protocol used by the source device or bus to the protocol used by the target device or bus.
In addition to providing an interface to an ISA/EISA bus for PCI bus 114, secondary bus bridge 116 may further incorporate additional functionality, as desired. An input/output controller (not shown), either external from or integrated with secondary bus bridge 116, may also be included within computer system 100 to provide operational support for a keyboard and mouse 122 and for various serial and parallel ports, as desired. An external cache unit (not shown) may further be coupled to CPU bus 124 between processor 10 and bus bridge 102 in other embodiments. Alternatively, the external cache may be coupled to bus bridge 102 and cache control logic for the external cache may be integrated into bus bridge 102. L2 cache 128 is further shown in a backside configuration to processor 10. It is noted that L2 cache 128 may be separate from processor 10, integrated into a cartridge (e.g. slot 1 or slot A) with processor 10, or even integrated onto a semiconductor substrate with processor 10.
Main memory 104 is a memory in which application programs are stored and from which processor 10 primarily executes. A suitable main memory 104 comprises DRAM (Dynamic Random Access Memory). For example, a plurality of banks of SDRAM (Synchronous DRAM) or Rambus DRAM (RDRAM) may be suitable. Main memory 104 may also include DDR DRAM.
PCI devices 112A-112B are illustrative of a variety of peripheral devices such as, for example, network interface cards, video accelerators, audio cards, hard or floppy disk drives or drive controllers, SCSI (Small Computer Systems Interface) adapters and telephony cards. Similarly, ISA device 118 is illustrative of various types of peripheral devices, such as a modem, a sound card, and a variety of data acquisition cards such as GPIB or field bus interface cards.
Graphics controller 108 is provided to control the rendering of text and images on a display 126. Graphics controller 108 may embody a typical graphics accelerator generally known in the art to render three-dimensional data structures which can be effectively shifted into and from main memory 104. Graphics controller 108 may therefore be a master of AGP bus 110 in that it can request and receive access to a target interface within bus bridge 102 to thereby obtain access to main memory 104. A dedicated graphics bus accommodates rapid retrieval of data from main memory 104. For certain operations, graphics controller 108 may further be configured to generate PCI protocol transactions on AGP bus 110. The AGP interface of bus bridge 102 may thus include functionality to support both AGP protocol transactions as well as PCI protocol target and initiator transactions. Display 126 is any electronic display upon which an image or text can be presented. A suitable display 126 includes a cathode ray tube (xe2x80x9cCRTxe2x80x9d), a liquid crystal display (xe2x80x9cLCDxe2x80x9d), etc.
It is noted that, while the AGP, PCI, and ISA or EISA buses have been used as examples in the above description, any bus architectures may be substituted as desired. It is further noted that computer system 100 may be a multiprocessing computer system including additional processors (e.g. processor 10a shown as an optional component of computer system 100). Processor 10a may be similar to processor 10. More particularly, processor 10a may be an identical copy of processor 10. Processor 10a may be connected to bus bridge 102 via an independent bus (as shown in FIG. 1) or may share CPU bus 124 with processor 10. Furthermore, processor 10a may be coupled to an optional L2 cache 128a similar to L2 cache 128.
Various embodiments of a circuit and method for shifting the level of a differential clock crossing point are disclosed. In one embodiment, a differential clock driver provides a pair of differential clock signals to a memory device configured to receive the differential clock signals and having a specified valid range for the crossing point of the differential clock signals. A level-shifting circuit is coupled to one or both of the differential clock signals and configured to shift the crossing point to lie within the valid range. The memory device may be DDR SDRAM.
In some embodiments, the level-shifting circuit may include a pull-up device. The pull-up device may, in some embodiments, include two pull-up resistors coupled to a voltage source, where one resistor is coupled to one of the differential clock signals and the other resistor is coupled to the other differential clock signal. The level-shifting device may include a pull-down device in some embodiments. The pull-down device may include two pull-down resistors coupled to ground, where one resistor is coupled to one of the differential clock signals and the other resistor is coupled to the other differential clock signal. In certain embodiments, the level-shifting device may include an active component.
In another embodiment, a computer system that includes a processor, a north bridge, one or more memory devices and a differential clock level-shifting circuit is disclosed. The north bridge is coupled to the processor by a first bus. The one or more memory devices are configured to receive a pair of differential clock signals and have a specified valid range for the crossing point of the pair of differential clock signals. The system memory devices may include DDR SDRAM in some embodiments. The differential clock level-shifting circuit is coupled to one or both of the differential clock signals and is configured to shift the crossing point to lie within the valid range.
A method for configuring a computer system is also disclosed. A pair of differential clock signals is provided to a memory device having a specified valid range for the crossing point of the differential clock signals. An actual differential clock crossing point is compared to a specified range for the crossing point. If the actual crossing point is not within the specified range, a level-shifting device is coupled to one or both of the differential clock signals. In some embodiments, the level-shifting device may be coupled to one or both of the differential clock signals even if the crossing point is already within the valid range so that the crossing point can be shifted closer to an ideal value.
A differential clocking circuit is also disclosed. A device is configured to receive a pair of differential clock signals and has a specified valid range for the crossing point of the differential clock signals. The differential clock signals are provided by a differential clock driver. A level-shifting circuit is coupled to one or both of the differential clock signals and is configured to shift the crossing point to lie within the valid range.